Diamond Semiconductor System and Method

ABSTRACT

Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The system may include a diamond material having n-type donor atoms and a diamond lattice, wherein 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K. The method of fabricating diamond semiconductors may include the steps of selecting a diamond material having a diamond lattice; introducing a minimal amount of acceptor dopant atoms to the diamond lattice to create ion tracks; introducing substitutional dopant atoms to the diamond lattice through the ion tracks; and annealing the diamond lattice.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of U.S. Provisional Application No.61/513,569, filed Jul. 30, 2011; U.S. application Ser. No. 13/273,467,filed Oct. 14, 2011; and U.S. application Ser. No. 14/581,030, filedDec. 23, 2014.

BACKGROUND Field

This invention is generally related to semiconductor systems andfabrication methods, and more particularly to a system and method forfabricating diamond semiconductors.

Background

Diamond possesses favorable theoretical semiconductor performancecharacteristics. However, practical diamond based semiconductor deviceapplications remain limited. One issue that has limited the developmentof practical diamond based semiconductors is the difficulty offabricating quality n-type layers in diamonds. While attempts have beenmade to improve n-type diamond fabrication based on limiting theconcentration of vacancy created defects, the difficulties associatedwith fabricating quality n-type layers in diamond has yet to besufficiently resolved. Therefore, there is a need for a new and improvedsystem and method for fabricating diamond semiconductors, includingn-type layers within diamond semiconductors.

SUMMARY

Disclosed herein is a new and improved system and method for fabricatingdiamond semiconductors. In accordance with one aspect of the approach,the system may include a diamond material having n-type donor atoms anda diamond lattice, wherein 0.16% of the donor atoms contributeconduction electrons with mobility greater than 770 cm²/Vs to thediamond lattice at 100 kPa and 300K.

In another aspect of the approach, a method of fabricating diamondsemiconductors may include the steps of selecting a diamond materialhaving a diamond lattice; introducing a minimal amount of acceptordopant atoms to the diamond lattice to create ion tracks; introducingsubstitutional dopant atoms to the diamond lattice through the iontracks; and annealing the diamond lattice, wherein the introduction ofthe minimal amount of acceptor dopant atoms does not create a criticaldensity of vacancies, and the introduction of the minimal amount ofacceptor dopant atoms diminishes the resistive pressure capability ofthe diamond lattice.

Other systems, methods, aspects, features, embodiments and advantages ofthe system and method for fabricating diamond semiconductors disclosedherein will be, or will become, apparent to one having ordinary skill inthe art upon examination of the following drawings and detaileddescription. It is intended that all such additional systems, methods,aspects, features, embodiments and advantages be included within thisdescription, and be within the scope of the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

It is to be understood that, the drawings are solely for purpose ofillustration. Furthermore, the components in the figures are notnecessarily to scale, emphasis instead being placed upon illustratingthe principles of the system disclosed herein. In the figures, likereference numerals designate corresponding parts throughout thedifferent views.

FIG. 1 is a block diagram of a first embodiment of the method forfabricating diamond semiconductors.

FIG. 2A is a perspective view of a prior art model of an intrinsicdiamond thin film wafer upon which the method of FIG. 1 may bepracticed.

FIG. 2B is a prior art model of an intrinsic diamond lattice structureof the diamond of FIG. 2A.

FIG. 3A is a perspective view of an exemplary model of a doped diamondthin film wafer such as may be fabricated by practicing the method ofFIG. 1 upon the intrinsic diamond thin film wafer of FIG. 2.

FIG. 3B is a model of a doped diamond lattice structure of the dopeddiamond thin film wafer of FIG. 3A.

FIG. 4 is a block diagram of a second embodiment of the method forfabricating diamond semiconductors.

FIG. 5A and FIG. 5B are block diagram of a third embodiment of themethod for fabricating diamond semiconductors.

FIG. 6 a top view of an exemplary P⁺-i-N diode model that may befabricated according to the method of FIG. 5A and FIG. 5B.

FIG. 7 is a perspective view of a model of an exemplary six-pin surfacemount device package that may be fabricated according to the method ofFIG. 5A and FIG. 5B.

FIG. 8 shows a schematic diagram of a diode test condition setup, suchas may be employed with the diode model of FIG. 6.

FIG. 9 is a graphical illustration of the threshold voltage performancecharacteristics of a diode that may be fabricated according to themethod of FIG. 5A and FIG. 5B.

FIG. 10 is a graphical illustration of the current-voltagecharacteristics of a diode that may be fabricated according to themethod of FIG. 5A and FIG. 5B in forward bias.

FIG. 11 is a graphical illustration of the current densitycharacteristics of a diode that may be fabricated according to themethod of FIG. 5A and FIG. 5B in forward bias.

FIG. 12 is a graphical illustration of the current-voltagecharacteristics of a diode, that may be fabricated according to themethod of FIG. 5A and FIG. 5B in reverse bias.

FIG. 13 is a graphical illustration of the current densitycharacteristics of a diode that may be fabricated according to themethod of FIG. 5A and FIG. 5B in reverse bias.

FIG. 14 shows a schematic illustration of an RF attenuator driver foruse with a diode that may be fabricated according to the method of FIG.5A and FIG. 5B.

DETAILED DESCRIPTION

The following detailed description, which references to and incorporatesthe drawings, describes and illustrates one or more specificembodiments. These embodiments, offered not to limit but only toexemplify and teach, are shown and described in sufficient detail toenable those skilled in the art to practice what is claimed. Thus, forthe sake of brevity, the description may omit certain information knownto those of skill in the art.

FIG. 1 shows a block diagram of a first embodiment of the method 100 forfabricating layers within diamond material. The method 100 may include afirst step 102 of selecting a diamond material having a diamond latticestructure. The diamond material is intrinsic diamond. Intrinsic diamondis diamond that has not been intentionally doped. Doping may introduceimpurities for the purpose of giving the diamond material electricalcharacteristics, such as, but not limited to, n-type characteristics andp-type characteristics. The diamond material may be a single crystal orpolycrystalline diamond.

FIG. 2A is a perspective view of a model of an intrinsic diamond thinfilm wafer 200. Though not limited to any particular diamond material,in one embodiment, the diamond material of method 100 is the intrinsicdiamond thin film wafer 200. The intrinsic diamond thin film wafer 200may include a diamond layer 202, a silicon dioxide layer (SiO₂) 204, anda silicon wafer layer 206. Diamond layer 202 may be, but is not limitedto, ultrananocrystalline diamond. The intrinsic diamond thin film wafer200 may be 100 mm in diameter. The diamond layer 202 may be a 1 μmpolycrystalline diamond having a grain size of approximately 200-300 nm.The silicon dioxide layer (SiO₂) 204 may be approximately 1 μm. Thesilicon wafer layer 206 may be approximately 500 μm Si, such as Aqua 100available from Advanced Diamond Technologies, Inc. The first step 102 ofmethod 100 may include selecting a variety of diamond base materialssuch as, but not limited to, the exemplary diamond layer 202 ofintrinsic diamond thin film wafer 200.

FIG. 2B is a model of an intrinsic diamond lattice structure 210, suchas, hut not limited to, an intrinsic diamond lattice structure ofdiamond layer 202. The intrinsic diamond lattice structure 210 mayinclude a plurality of carbon atoms 212. The intrinsic diamond latticestructure 210 is known to those having skill in the art. In the model,the intrinsic diamond lattice structure 210 is shown defect free and allof the atoms shown are carbon atoms 212.

The second step 104 of method 100 may include introducing a minimalamount of acceptor dopant atoms to the diamond lattice to create iontracks (shown in FIG. 3 as bounded by the lines 320). The creation ofthe ion tracks may include creation of a non-critical concentration ofvacancies, for example, less than 10²²/cm³ for single crystal bulkvolume, and a diminution of the resistive pressure capability of thediamond layer 202. For example, second step 104 may include introducingthe acceptor dopant atoms using ion implantation at approximately 293 to298 degrees Kelvin (K) in a low concentration. The acceptor dopant atomsmay be p-type acceptor dopant atoms. The p-type dopant may be, but isnot limited to, boron, hydrogen and lithium. The minimal amount ofacceptor dopant atoms may be such that carbon dangling bonds willinteract with the acceptor dopant atoms, but an acceptor level is notformed in the diamond lattice.

The minimal amount of acceptor dopant atoms of second step 104 may befor example, but is not limited to, approximately 1×10¹⁰/cm² of boron.In other embodiments, the minimal amount of acceptor dopant atoms ofsecond step 104 may be for example, but is not limited to, approximately5×10¹⁰/cm² of boron and a range of 1×10⁸/cm² to 5×10¹⁰/cm². Second step104 may be accomplished by boron co-doping at room temperature in thatcreated vacancies may be mobile, but boron may take interstitialpositioning. The second step 104 may create mobile vacancies forsubsequent dopants, in addition to some substitutional positioning.

The ion tracks of second step 104 may be viewed as a ballistic pathwayfor introduction of larger substitutional dopant atoms (see third step106 below). Second step 104 may also eliminate the repulsive force (withrespect to the substitutional dopant atoms (see step 106 below)) of thecarbon dangling bonds in the diamond lattice by energetically favoringinterstitial positioning of the acceptor dopant atoms, and altering thelocal formation energy dynamics of the diamond lattice.

The third step 106 of method 100 may include introducing thesubstitutional dopant atoms to the diamond lattice through the iontracks. For example, third step 106 may include introducing the largersubstitutional dopant atoms using ion implantation preferably at orbelow approximately 78 degrees K for energy implantation at less than500 keV. Implanting below 78 degrees K may allow for the freezing ofvacancies and interstitials in the diamond lattice, while maximizingsubstitutional implantation for the substitutional dopant atoms. Thelarger substitutional dopant atoms may be for example, but is notlimited to, phosphorous, nitrogen, sulfur and oxygen.

For implantation where the desired ion energy is higher, as localself-annealing may occur, it may be beneficial to use ambienttemperature in conjunction with MeV energy implantation. Where thedesired ion energy is higher, there may be a higher probability of anincoming ion taking substitutional positioning.

The larger substitutional dopant atoms may be introduced at a muchhigher concentration than the acceptor dopant atoms. The higherconcentration of the larger substitutional dopant atoms may be, but isnot limited to, approximately 9.9×10¹⁷/cm³ of phosphorous and a range of8×10¹⁷ to 2×10¹⁸/cm³.

In third step 106, the existence of the ballistic pathway andminimization of negative repulsive forces acting on the substitutionaldopant atoms facilitates the entry of the substitutional dopant atomsinto the diamond lattice with minimal additional lattice distortion. Ionimplantation of the substitutional dopant atoms at or belowapproximately 78 degrees K provides better impurity positioning,favoring substitutional positioning over interstitial positioning, andalso serves to minimize the diamond lattice distortions because fewervacancies are created per impinging ion.

In one embodiment, ion implantation of step 106 may be performed at 140keV, at a 6 degree offset to minimize channeling. Implant beam energymay be such that dosages overlap in an active implant area approximately25 nm below the surface so that graphitic lattice relaxation isenergetically unfavorable. Doping may be performed on a Varian IonImplantation System with a phosphorus mass 31 singly ionized dopant(i.e., 31P+); a beam current of 0.8 μA; a beam energy of 140 keV; a beamdose 9.4×10¹¹/cm²; an incident angle of 6 degrees; and at a temperatureof at or below approximately 78 degrees K.

The fourth step 108 of method 100 may include subjecting the diamondlattice to rapid thermal annealing. The rapid thermal annealing may bedone at 1000 degree celsius C. Rapid thermal annealing may restoreportions of the diamond lattice that may have been damaged during thesecond step 104 and the third step 106 and may electrically activate theremaining dopant atoms that may not already be substitutionalpositioned. Higher temperatures at shorter time durations may be morebeneficial than low temperature, longer duration anneals, as the damagerecovery mechanism may shift during long anneal times at temperatures inexcess of 600 C.

FIG. 3A is a perspective view of a model of a doped diamond thin filmwafer 300, such as may be fabricated by subjecting the intrinsic diamondthin film wafer 200 to method 100. The doped diamond thin film wafer 300may include a doped diamond layer 302, the silicon dioxide layer (SiO₂)204, and the silicon wafer layer 206.

FIG. 3B is a model of a doped diamond lattice structure 304, such as maybe the result of subjecting the diamond layer 202 to method 100. Thedoped diamond lattice structure 304 may include a plurality of carbonatoms 314, a plurality of phosphorus atoms 306, and a plurality ofvacancies 308, and a boron atom 312.

The method 100 allows for the fabrication of a semiconductor systemincluding a diamond material, such as, but not limited to, the dopeddiamond thin film wafer 300, having n-type donor atoms, such as, but notlimited to, the plurality of phosphorus atoms 306, and a diamondlattice, such as, but not limited to, the doped diamond latticestructure 304, wherein, for example by way of shallow ionization energy,approximately 0.25 eV, 0.16% of the donor atoms contribute conductionelectrons with mobility greater than 770 cm2/Vs to the diamond latticeat 100 kPa and 300K.

FIG. 4 shows a block diagram of a second embodiment of the method 400for fabricating layers within diamond material. The first step of method400 may be the same as the first step 102 of method 100, which includesselecting a diamond material having a diamond lattice structure.

The second step 402 of method 400 may include cleaning the diamondmaterial to remove surface contaminants. For example, second step 402may include cleaning the intrinsic diamond thin film wafer 200 (see FIG.2). The cleaning may be a strong clean, for example but not limited to,a standard diffusion clean, known to those having skill in the art. Oneexample, of such a diffusion clean includes: applying a 4:1 solution ofH₂SO₄/H₂O₂ for 10 minutes; applying a solution of H₂O₂ for 2.5 minutes;applying a 5:1:1 solution of H₂O/H₂O₂/HCL for 10 minutes; applying asolution of H₂O₂ for 2.5 minutes; and heat spin drying for 5 minutes.

The third step 404 of method 400 may include subjecting the diamondmaterial to a pre-ion track mask deposition over a first portion of thediamond lattice. The pre-ion track mask may protect a first portion ofthe diamond material during ion implantation. The pre-ion track maskdeposition may be an aluminum pre-implant mask deposition. The pre-iontrack mask deposition may be performed using a Gryphon Metal SputterSystem using aluminum of 99.99999% (6N) purity, with a deposition timeof 21-24 seconds, at a power of 7.5 kW, a pressure: 2.5×10⁻³ Torr; andto a thickness of 30 nm.

The fourth step of method 400 may be the same as the second step 104 ofmethod 100, which includes introducing a minimal amount of acceptordopant atoms to the diamond lattice to create ion tracks.

The fifth step of method 400 may be the same as the third step 106 ofmethod 100, which includes introducing substitutional dopant atoms tothe diamond lattice through the ion tracks.

The sixth step 406 of method 400 may include mask etching, cleaning, andannealing the diamond lattice. The mask etching may be an aluminum masketch. The mask etching may be a wet etch using aluminum etchant, forexample, a Cyantek AL-11 Aluminum etchant mixture or an etchant having acomposition of 72% phosphoric acid; 3% acetic acid; 3% nitric acid; 12%water; and 10% surfactant, at a rate of 1 μm per minute. After thealuminum is removed visually, which may take approximately 30 seconds,the wafers may be run under de-ionized water for sixty seconds and driedvia pressurized air gun.

In other embodiments, the mask etching of the sixth step 406 may be ablanket etch using reactive ion etching (Ar (35 SCCM)/O₂ (10 SCCM), atV_(BIAS) 576 V, 250 W Power, under pressure of 50 mTorr, for a totaletch thickness of 25 nm. The Ar/O₂ etch may have a dual function of bothetching and polishing/terminating the diamond material surface. Inaddition to initial etching, the same process recipe is laterimplemented to form device architecture, and define different active andinactive areas of the diamond, as per required by end application use(i.e., MOSFET, diode, LED, etc.). Etch masking layer, for example a 200nm thick aluminum deposition, may be formed via standard E-beamevaporation. Etching may be performed on an Oxford System 100 PlasmalabEquipment (Oxford Deep Reactive Ion Etcher). The etching conditions maybe: RIE Power: 200 W; ICP power: 2000 W; Pressure: 9 mTorr; O₂ flow: 50sccm; Ar flow: 1 sccm. The etching rates may be 155 nm/min for thediamond layer and 34 nm/min for the aluminum masking layer.

The cleaning of sixth step 406 may be similar to diffusion cleandescribed in the second step 402. The annealing of sixth step 406 may bea rapid thermal annealing to approximately 1000-1150 degrees Celsiusunder flowing N₂ for approximately 5 minutes and/or the rapid thermalannealing may be performed with an Agilent RTA model AG4108 operatingunder the settings shown in Table 1,

TABLE 1 Command Time(s)/Intensity (%) Temperature Gas Flow Delay 20 sN/A 10 SLPM N₂  Delay  5 s N/A 7 SLPM N₂ Inin 8%  25° C. 4 SLPM N₂ Ramp10 s 650° C. 4 SLPM N₂ Steady 15 s 650° C. 4 SLPM N₂ Ramp 10 s 900° C. 4SLPM N₂ Steady 55 s 950° C. 4 SLPM N₂ Ramp 30 s 650° C. 7 SLPM N₂ Delay15 s N/A 7 SLPM N₂

The sixth step 406 of method 400 may include subjecting the diamondmaterial to a pre-substitutional mask deposition over a portion of thediamond lattice. The pre-substitutional mask deposition may be analuminum pre-implant mask deposition. The pre-substitutional maskdeposition may be performed using a Gryphon Metal Sputter System usingaluminum of 99.99999% (6N) purity, with a deposition time of 21-24seconds, at a power of 7.5 kW, a pressure: 2.5×10⁻³ Torr; and to athickness of 30 nm.

For some applications, it may be beneficial to differentially dopedifferent parts of the same diamond wafer, for example, to create p-typeand n-type regions. In embodiments, various semiconductor devices arecreated including P-N junctions and P-i-N junctions.

FIG. 5A and FIG. 5B show a block diagram of a third embodiment of themethod 500 for fabricating layers within diamond material. Method 500provides a process for fabricating n-type layers within diamondsemiconductors for a P⁺-i-N diode. The first step of method 500 may bethe same as the first step 102 of method 100, which includes selecting adiamond material having a diamond lattice structure.

FIG. 6 shows a top view of an exemplary model of a P⁺-i-N diode 600 thatmay be fabricated according to method 500. P⁺-i-N diode 600 may includea lightly doped semiconductor region (i) (for example, see FIG. 8, 804),between a pt-type semiconductor region 608, and an n-type semiconductorregion 606. The method of 500 with SRIM, Stopping and Range of ions inMatter, modeling provides a path for fabricating P⁺-i-N diodes thatapproach theoretical projections. In one embodiment, the P⁺-i-N diode600 may include the lightly doped semiconductor region (i) 804 of adepth of approximately 10 nm, between a p-type semiconductor (forexample, see FIG. 8, 806) of a depth of approximately 150 nm, thep⁺-type semiconductor region 608 of a depth of approximately 100 nm, andthe n-type semiconductor region 606 of a depth of approximately 100 nm.6 also shows a metallic contact/bonding pad 604 for connecting to thep⁺-type semiconductor region 608.

The second step of method 500 may be the same as the second step 402 ofmethod 400, including cleaning the diamond material to remove surfacecontaminants.

The third step 502 of method 500 may include subjecting the diamondmaterial to a pre-P⁺ mask deposition over a non-P⁺ portion of thediamond lattice. The pre-P⁺ mask deposition may protect a non-P⁺ portionof the diamond material during P⁺ ion implantation. The pre-P⁺ maskdeposition may be an aluminum pre-implant mask deposition. The pre-iontrack mask deposition may be performed using a Gryphon Metal SputterSystem using aluminum of 99.99999% (6N) purity, with a deposition timeof 21-24 seconds, at a power of 7.5 kW, a pressure: 2.5×10⁻³ Torr; andto a thickness of 30 nm.

The fourth step 504 of method 500 may include a P⁺ layer implant of thediamond material. The P⁺ layer implant may be performed with a dopant of11B⁺, at a beam current of 0.04 μA, at a beam energy of 55 keV, with abeam dose of 1×10²⁰ atoms/cm², at an incident angle of 6 degrees, and ator below approximately 78 degrees K, to create a P⁺ layer of 100 nm.

The fifth step of method 500 may be the same as the sixth step 406 ofmethod 400, including mask etching, cleaning, and annealing the diamondmaterial.

The sixth step 506 of method 500 may include subjecting the diamondmaterial to a pre-P mask deposition over a non-P portion of the diamondlattice. The pre-P mask deposition may protect a non-P portion of thediamond material during P ion implantation. The pre-P mask depositionmay be an aluminum pre-implant mask deposition. The pre-P maskdeposition may be performed using a Gryphon Metal Sputter System usingaluminum of 99.99999% (6N) purity, with a deposition time of 21-24seconds, at a power of 7.5 kW, a pressure: 2.5×10⁻³ Torr; and to athickness of 30 nm.

The seventh step 508 of method 500 may include a P layer implant of thediamond material. The P layer implant may be performed with a dopant of11B⁺, at a beam current of 0.04 μA, at a beam energy of 55 keV, with abeam dose of 3×10¹⁷ atoms/cm², at an incident angle of 6 degrees, and ator below approximately 78 degrees K, to create a P layer of 150 nm.

The eighth step of method 500 may be the same as the sixth step 406 ofmethod 400, including mask etching, cleaning, and annealing the diamondmaterial.

The ninth step of method 500 may be the same as the third step 404 ofmethod 400, including subjecting the diamond material to a pre-ion trackmask deposition over a first portion of the diamond lattice.

The tenth step of method 500 may be the same as the second step 104 ofmethod 100, which includes introducing a minimal amount of acceptordopant atoms to the diamond lattice to create ion tracks.

The eleventh step of method 500 may be the same as the third step 106 ofmethod 100, which includes introducing substitutional dopant atoms tothe diamond lattice through the ion tracks.

The twelfth step of method 500 may be same as the sixth step 406 ofmethod 400, including mask etching, cleaning, and annealing the diamondmaterial.

The thirteenth step 510 of method 500 may include a blanket etch. Thethirteenth step 510 may include a blanket etch in which the surfacelayer, approximately 25 nm, of the diamond layer 202 is etched off toremove any surface graphitization.

The fourteenth step 512 of method 500 may include aphotolithography/mesa etch to obtain a diamond stack structure, such asthat shown in FIG. 6. The fourteenth step 512 may include a diffusionclean and photolithography prior to the mesa etch.

The fifteenth step 514 of method 500 may include a creating a contactfor the top of the stack. Contact to the top of the stack may beachieved by evaporating ITO with 5N purity to a thickness of 200 nm ontothe stack through a shadow mask and then performing a liftoff.

The sixteenth step 516 of method 500 may include annealing. Theannealing of step 516 may be oven annealing at 420 degrees C. in Arambient until ITO transparency is attained, which may be inapproximately 2.5 hours.

The seventeenth step 518 of method 500 may include creating ohmiccontacts. The ohmic contacts may include contacts to the layer, forexample, the metallic contact/bonding pad 604, and the n-layer. As wirebonding may be difficult with a small contact area, Ti and Au layers maybe evaporated through a shadow mask using photolithography. Ti may alsofunction as a diffusion barrier between ITO and Au layers. A contactlayer thickness of 30 nm may be created for the P layer. A contact layerthickness of 200 nm may be created for the N-layer. In one embodiment,the diamond cap layer may be removed to expose the newly formed n-typelayer to form an electrical contact for device use. The step may includepolishing the diamond layer while etching, thus minimizing the surfaceroughness, and electrically terminating (oxygen) the surface of thediamond, a step in semiconductor device fabrication. In someembodiments, there is a further step of forming metal contacts on thediamond so that the diamond may function as a component part of anelectronic device. The seventeenth step 518 of method 500 may include ametal furnace annealing. The metal furnace annealing may be performed at420 degrees celsius for two hours.

The eighteenth step 520 of method 500 may include wafer surfacetermination.

The nineteenth step 522 of method 500 may include wafer surface dicing.

The twentieth step 524 of method 500 may include packaging. In thetwentieth step 520, portions of the diamond material may be diced,mounted, wire bound and encapsulated in transparent silicone sealant tocreate 6-pin surface mount device packages.

FIG. 7 shows a perspective view of a model of an exemplary six-pinsurface mount device package 700 that may be fabricated according to themethod of FIG. 5A and FIG. 5B.

The methods disclosed herein may allow for the creation of a number ofelectrical diamond junctions to serve functions traditionally served bysilicon semiconductors. While the application discusses examples in thecontext of a bipolar diode, those having skill in the art will recognizethat the present techniques describe novel genuine n-type diamondmaterial and novel p-type diamond material that may be used in multiplevariations of electrical devices and monolithically formed combinationsof the variations, including FETs and other switches, digital andanalog, and light emitting bodies, and are not limited to the specificimplementations shown herein. The various preferred embodiments need notnecessarily be separate from each other and can be combined.

FIG. 8 shows a schematic diagram of a P⁺-i-N diode test condition setup802. A P⁺-i-N diode, such as a P⁺-i-N diode 600 fabricated according tomethod 500, may be tested according to the P⁺-i-N diode test conditionsetup 802.

FIG. 9 is a graphical illustration 900 of the threshold voltageperformance characteristics 902 of a P⁺-i-N diode that may be fabricatedaccording to method 500. The threshold voltage performancecharacteristics 902 may be obtained based upon DC conditions usingsuitable resistor biasing, and RF′ conditions using suitable TTL driversor hybrid wire configuration, at room temperature, 76 degrees F. by IRmeasurement, under both low field and high field conditions. Thethreshold voltage performance characteristics 902 indicates a thresholdvoltage and current levels similar to those theoretically predicted fordiamond.

FIG. 10 is a graphical illustration 1000 of the current-voltagecharacteristics of a P⁺-i-N diode, such as a P⁺-i-N diode 600 fabricatedaccording to method 500, in forward bias, with the cathode negative, atroom temperatures. A current-voltage curve 1002 shows thecurrent-voltage characteristics for such a P⁺-i-N diode that may befabricated according to method 500. The current-voltage curve 1002indicates a large concentration of electrons are available forconduction at room temperatures. A low voltage depletion region 1004 ofthe current-voltage curve 1002 shows charge carriers are diffused fromthe N layer and the P layer into the intrinsic region, for example,charge carriers are diffused from the n-type semiconductor region 606and the between a p⁺-type semiconductor region 608, into the lightlydoped semiconductor region (i) 804. In the lightly doped semiconductorregion (i) 804 the charge carriers may combine. Since recombination doesnot occur instantly, charge may be stored in the lightly dopedsemiconductor region (i) 804, thus lowering resistivity.

A high injection region 1006 of the current-voltage curve 1002 showsthat as an applied potential is increased, charge carriers may floodinto the intrinsic region, for example the lightly doped semiconductorregion (i) 804, resulting in a concentration of carriers in excess ofequilibrium concentrations. A series resistance region 1008 of thecurrent-voltage curve 1002 is also shown.

FIG. 11 is a graphical illustration 1100 of the current densitycharacteristics of a P⁺-i-N diode, such as a P⁺-i-N diode 600 fabricatedaccording to method 500, in forward bias, with the cathode negative, atroom temperatures. A current density curve 1102 shows the currentdensity characteristics for such a P⁺-i-N diode that may be fabricatedaccording to method 500. The current density curve 1102 shows aconcentration of charge carrier types at current densities of greaterthan 1600 Amperes/cm² at 5 V.

FIG. 12 is a graphical illustration 1200 of the current-voltagecharacteristics of a P⁺-i-N diode, such as a P⁺-i-N diode 600 fabricatedaccording to method 500, in reverse bias, with the cathode positive, atroom temperatures. A current-voltage curve 1202 shows thecurrent-voltage characteristics for such a P⁺-i-N diode that may befabricated according to method 500. The current-voltage curve 1202 showsthat a small amount of reverse voltage may be required before thedepletion region width becomes fully depleted of charge carriers andcarrier diffusion ceases, as indicated by the small rise and rapiddecrease in current levels.

FIG. 13 is a graphical illustration 1300 of the current densitycharacteristics of a P⁺-i-N diode, such as a P⁺-i-N diode 600 fabricatedaccording to method 500, in reverse bias, with the cathode positive, atroom temperatures. A current density curve 1302 shows the currentdensity characteristics for such a P⁺-i-N diode that may be fabricatedaccording to method 500. The current density curve 1302 shows a a P⁺-i-Ndiode, such as a P⁺-i-N diode 600, is suited for signal attenuation,such as but not limited, to RI signal attenuation, as modulation iscontrollable.

FIG. 14 shows a schematic illustration of an RF attenuator driver chipconfiguration 1400, for use with a P⁺-i-N diode, such as a P⁺-i-N diode600 fabricated according to method 500. RF attenuator 1400 may provideattenuation characteristics with R_(load) varying from approximately 10KΩ to 1 mΩ, current controlled characteristic, at 77 KHz.

The systems and fabrication methods described herein provide a number ofnew and useful technologies, including novel n-type and novel p-typediamond semiconducting materials and devices, and methods forfabricating novel n-type and novel p-type diamond semiconductingmaterials and devices.

The novel fabrication methods include, but are not limited to, those forcreating, etching, and metalizing (Schottky and Ohmic) genuine qualityn-type diamond material; creating Integrated. Circuits (ICs) and devicedrivers from diamond based power elements.

The novel devices include, but are not limited to, n-type diamondsemiconductors that are at least partially activated at roomtemperature—i.e., the device material has sufficient carrierconcentration to activate and participate in conduction; n-type diamondwith high electron mobility; n-type diamond which has both high carriermobility and high carrier concentration—without requiring a hightemperature (above room temperature) or the presence of a highelectrical field; an n-type diamond semiconductor with an estimatedelectron mobility in excess of 1,000 cm²/Vs and a carrier concentrationof approximately 1×10¹⁶ electrons/cm³ at room/ambient temperature; abipolar diamond semiconductor device; devices with p-type and n-typeregions on a single diamond wafer; diamond diode devices; bipolardiamond semiconductor devices carrying high current withoutnecessitating either a high temperature or the presence of a strongelectrical field; bipolar diamond semiconductor devices which can carrya one milliamp current while at room temperature and in the presence ofa 0.28V electrical field; an n-type diamond material on polycrystallinediamond; a low cost thin film polycrystalline diamond-on-siliconcarrier; diamond semiconductors on other carrier types (e.g., FusedSilica, Quartz, Sapphire, Silicon Oxide or other Oxides, etc.); adiamond power RF attenuator, a polycrystalline diamond power RFattenuator chip, a polycrystalline diamond power RF attenuator device; adiamond light emitting diode or/laser diode (LED); monolithicallyintegrate diamond based logic drivers with high power elements (e.g.,LED) on the same chip; n-type diamond material which is stable in thepresence of oxygen (i.e., if a non-negligible amount of oxygen ispresent on the surface (such as when the wafer is on open air) then-type semiconductor's conductivity and performance continue).

In some embodiments, this n-type and novel p-type diamond semiconductingmaterial is constructed using polycrystalline diamond having less than amicrometer size grain and with doped thin film layers having sizes onthe order of less than 900 nm. The techniques for forming said diamondmaterial may be used on diamond films with diamond grain boundaries thatare nearly atomic abrupt, such that uniformity of electrical performancemay be maintained, while enabling the ability to form thin-film featuresfrom said material.

Another aspect of the invention is the ability to create metal contactsattached to the diamond semiconducting material, including the n-typematerial. Said metal contacts attach to the diamond material andcontinue to have good/ohmic conductivity (e.g., displaying highlinearity). Metal contacts may refer to either or both metals (e.g., Au,Ag, Al, Ti, Pd, Pt, etc.) or transparent metals (e.g., indium tin oxide,fluoride tin oxide, etc.), as warranted by desired application use.

The word “exemplary” is used herein to mean “serving as an example,instance, or illustration.” Any embodiment or variant described hereinas “exemplary” is not necessarily to be construed as preferred oradvantageous over other embodiments or variants. All of the embodimentsand variants described in this description are exemplary embodiments andvariants provided to enable persons skilled in the art to make and usethe invention, and not necessarily to limit the scope of legalprotection afforded the appended claims.

The above description of the disclosed embodiments is provided to enableany person skilled in the art to make or use that which is defined bythe appended claims. The following claims are not intended to be limitedto the disclosed embodiments. Other embodiments and modifications willreadily occur to those of ordinary skill in the art in view of theseteachings. Therefore, the following claims are intended to cover allsuch embodiments and modifications when viewed in conjunction with theabove specification and accompanying drawings.

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 5. A method of fabricating diamond semiconductors, the method including the steps of: selecting a diamond material having a diamond lattice, forming a diamond layer on a silicon dioxide layer; introducing acceptor dopant atoms to the diamond lattice to create pathways; introducing substitutional dopant atoms to the diamond lattice through the pathways; and annealing the diamond lattice to remove the pathways; wherein the introduction of the acceptor dopant atoms does not create a critical density of more than 10²²/cm³ of vacancies in the diamond layer.
 6. The method of claim 5, wherein the diamond material is intrinsic diamond.
 7. The method of claim 5, wherein the acceptor dopant atoms are introduced at 293 to 298 degrees Kelvin.
 8. The method of claim 5, wherein the acceptor dopant, atoms are boron.
 9. The method of claim 5, wherein the amount of acceptor dopant atoms is between 5×10⁸/cm² and 5×10¹⁰/cm².
 10. The method of claim 5, wherein the substitutional dopant atoms are introduced at or below 78 degrees Kelvin.
 11. The method of claim 5, wherein the substitutional dopant atoms are introduced at less than 500 keV.
 12. The method of claim 5, wherein the substitutional dopant atoms are introduced at less than 140 keV and at a 6 degree offset.
 13. The method of claim 5, wherein the substitutional dopant atoms are phosphorus.
 14. The method of claim 5, wherein the substitutional dopant atoms are introduced at a concentration greater than 9×10¹⁷/cm³.
 15. The method of claim 5, wherein the annealing takes place at or above 1000 degrees Celsius.
 16. A semiconductor fabricated according to the method of claim
 5. 